Broadband Packet Switching Technologies A Practical Guide to ATM Switches and IP Routers,9780471004547

Broadband Packet Switching Technologies A Practical Guide to ATM Switches and IP Routers

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Edition: 1st
ISBN13: 9780471004547
ISBN10: 0471004545
Format: Hardcover
Pub. Date: 2001-10-11
Publisher(s): Wiley-Interscience
List Price: $201.54

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Summary

The effective design of high-speed, reliable switching systems is essential for moving the huge volumes of traffic and multimedia over modern communications networks. This book explains all the main packet-switching architectures, including all theoretical and practical topics relevant to the design and management of high-speed networks. Delivering the most systematic coverage available of the subject, the authors interweave fundamental concepts with real-world applications and include engineering case studies from wireless and fiber-optic communications. Market: Hardware and Software Engineers in the telecommunication industry, System Engineers, and Technicians.

Author Biography

H. JONATHAN CHAO, PhD, earned his doctorate at The Ohio State University. Since 1992 he has been Professor of Electrical Engineering at Polytechnic University, Brooklyn, New York and conducts research in terabit ATM switches and IP routers, quality of service control, and photonic packet switching. He was co-founder and Chief Technical Officer of Coree Networks Inc., building a terabit IP/MPLS switch router. Between 1985 and 1992 he was a member of technical staff at Telcordia in New Jersey. He is a Fellow of the IEEE and has published widely in the above subjects.

Table of Contents

Preface xiii
Introduction
1(14)
ATM Switch Systems
3(5)
Basics of ATM networks
3(2)
ATM switch structure
5(3)
IP Router Systems
8(5)
Functions of IP routers
8(1)
Architectures of IP routers
9(4)
Design Criteria and Performance Requirements
13(2)
References
14(1)
Basics of Packet Switching
15(34)
Switching Concepts
17(4)
Internal link blocking
17(1)
Output port contention
18(1)
Head-of-line blocking
19(1)
Multicasting
19(1)
Call splitting
20(1)
Switch Architecture Classification
21(16)
Time division switching
22(2)
Space division switching
24(10)
Buffering strategies
34(3)
Performance of Basic Switches
37(12)
Input-buffered switches
37(3)
Output-buffered switches
40(4)
Completely shared-buffer switches
44(2)
References
46(3)
Input-Buffered Switches
49(34)
A Simple Switch Model
50(3)
Head-of-line blocking phenomenon
51(1)
Traffic models and related throughput results
52(1)
Methods for Improving Performance
53(4)
Increasing internal capacity
53(1)
Increasing scheduling efficiency
54(3)
Scheduling Algorithms
57(15)
Parallel iterative matching (PIM)
58(2)
Iterative round-robin matching (iRRM)
60(1)
Iterative round-robin with SLIP (iSLIP)
60(2)
Dual round-robin matching (DRRM)
62(3)
Round-robin greedy scheduling
65(2)
Design of round-robin arbiters/selectors
67(5)
Output-Queuing Emulation
72(6)
Most-Urgent-Cell-First-Algorithm (MUCFA)
72(1)
Chuang et al.'s results
73(5)
Lowest-Output-Occupancy-Cell-First Algorithm (LOOFA)
78(5)
References
80(3)
Shared-Memory Switches
83(20)
Linked-List Approach
84(7)
Content-Addressable Memory Approach
91(2)
Space-Time-Space Approach
93(1)
Multistage Shared-Memory Switches
94(3)
Washington University gigabit switch
95(1)
Concentrator-based growable switch architecture
96(1)
Multicast Shared-Memory Switches
97(6)
Shared-memory switch with a multicast logical queue
97(1)
Shared-memory switch with cell copy
98(1)
Shared-memory switch with address copy
99(2)
References
101(2)
Banyan-Based Switches
103(38)
Banyan Networks
103(3)
Batcher-Sorting Network
106(4)
Output Contention Resolution Algorithms
110(2)
Three-phase implementation
110(1)
Ring reservation
110(2)
The Sunshine Switch
112(2)
Deflection Routing
114(11)
Tandem banyan switch
114(3)
Shuffle-exchange network with deflection routing
117(1)
Dual shuffle-exchange network with error-correcting routing
118(7)
Multicast Copy Networks
125(16)
Broadcast banyan network
127(2)
Encoding process
129(3)
Concentration
132(1)
Decoding process
133(1)
Overflow and call splitting
133(1)
Overflow and input fairness
134(4)
References
138(3)
Knockout-Based Switches
141(48)
Single-Stage Knockout Switch
142(8)
Basic architecture
142(2)
Knockout concentration principle
144(2)
Construction of the concentrator
146(4)
Channel Grouping Principle
150(4)
Maximum throughput
150(2)
Generalized knockout principle
152(2)
A Two-Stage Multicast Output-Buffered ATM Switch
154(15)
Two-stage configuration
154(3)
Multicast grouping network
157(3)
Translation tables
160(3)
Multicast knockout principle
163(6)
A Fault-Tolerant Multicast Output-Buffered ATM Switch
169(16)
Fault model of switch element
169(3)
Fault detection
172(2)
Fault location and reconfiguration
174(7)
Performance analysis of reconfigured switch module
181(4)
Appendix
185(4)
References
187(2)
The Abacus Switch
189(38)
Basic Architecture
190(3)
Multicast Contention Resolution Algorithm
193(4)
Implementation of Input Port Controller
197(1)
Performance
198(10)
Maximum throughput
199(4)
Average delay
203(3)
Cell loss probability
206(2)
ATM Routing and Concentration Chip
208(3)
Enhanced Abacus Switch
211(9)
Memoryless multistage concentration network
212(2)
Buffered multistage concentration network
214(3)
Resequencing cells
217(2)
Complexity comparison
219(1)
Abacus Switch for Packet Switching
220(7)
Packet interleaving
220(2)
Cell interleaving
222(2)
References
224(3)
Crosspoint-Buffered Switches
227(12)
Overview of Crosspoint-Buffered Switches
228(1)
Scalable Distributed Arbitration Switch
229(5)
SDA structure
229(2)
Performance of SDA switch
231(3)
Multiple-Qos SDA Switch
234(5)
MSDA structure
234(2)
Performance of MSDA switch
236(2)
References
238(1)
The Tandem-Crosspoint Switch
239(14)
Overview of Input-Output-Buffered Switches
239(2)
TDXP Structure
241(5)
Basic architecture
241(1)
Unicasting operation
242(4)
Multicasting operation
246(1)
Performance of TDXP Switch
246(7)
References
252(1)
Clos-Network Switches
253(26)
Routing Properties and Scheduling Methods
255(3)
A Suboptimal Straight Matching Method for Dynamic Routing
258(1)
The ATLANTA Switch
259(4)
Basic architecture
261(1)
Distributed and random arbitration
261(1)
Multicasting
262(1)
The Continuous Round-Robin Dispatching Switch
263(5)
Basic architecture
264(1)
Concurrent round-robin dispatching (CRRD) scheme
265(2)
Desynchronization effect of CRRD
267(1)
The Path Switch
268(11)
Homogeneous capacity and route assignment
272(2)
Heterogeneous capacity assignment
274(3)
References
277(2)
Optical Packet Switches
279(58)
All-Optical Packet Switches
281(3)
The staggering switch
281(1)
ATMOS
282(1)
Duan's switch
283(1)
Optoelectronic Packet Switches
284(7)
HYPASS
284(2)
STAR-TRACK
286(1)
Cisneros and Brackett's Architecture
287(2)
BNR switch
289(1)
Wave-mux switch
290(1)
The 3M Switch
291(10)
Basic architecture
291(3)
Cell delineation unit
294(2)
VCI-overwrite unit
296(1)
Cell synchronization unit
297(4)
Optical Interconnection Network for Terabit IP Routers
301(36)
Introduction
301(2)
A terabit IP router architecture
303(3)
Router module and route controller
306(3)
Optical interconnection network
309(6)
Ping-pong arbitration unit
315(9)
OIN complexity
324(2)
Power budget analysis
326(2)
Crosstalk analysis
328(3)
References
331(6)
Wireless ATM Switches
337(28)
Wireless ATM Structure Overviews
338(3)
System considerations
338(11)
Wireless ATM protocol
349
Wireless ATM Systems
341(3)
NEC's WATMnet prototype system
341(1)
Olivetti's radio ATM LAN
342(1)
Virtual connection tree
342(1)
BAHAMA wireless ATM LAN
343(1)
NTT's wireless ATM Access
343
Other European projects
243(101)
Radio Access Layers
344(3)
Radio physical layer
344(2)
Medium access control layer
346(1)
Data link control layer
346(1)
Handoff in Wireless ATM
347(5)
Connection rerouting
348
Buffering
340(11)
Cell routing in a COS
351(1)
Mobility-Support ATM Switch
352(13)
Design of a mobility-support switch
353(5)
Performance
358(4)
References
362(3)
IP Route Lookups
365(74)
IP Router Design
366(3)
Architectures of generic routers
366(2)
IP route lookup design
368(1)
IP Route Lookup Based on Caching Technique
369(1)
IP Route Lookup Based on Standard Trie Structure
369(3)
Patricia Tree
372(1)
Small Forwarding Tables for Fast Route Lookups
373(4)
Level 1 of data structure
374(2)
Levels 2 and 3 of data structure
376(1)
Performance
377(1)
Route Lookups in Hardware at Memory Access Speeds
377(4)
The DIR-24-8-BASIC scheme
378(3)
Performance
381(1)
IP Lookups Using Multiway Search
381(7)
Adapting binary search for best matching prefix
381(3)
Precomputed 16-bit prefix table
384(1)
Multiway binary search: exploiting the cache line
385(3)
Performance
388(1)
IP Route Lookups for Gigabit Switch Routers
388(8)
Lookup algorithms and data structure construction
388(7)
Performance
395(1)
IP Route Lookups Using Two-Trie Structure
396(13)
IP route lookup algorithm
397(1)
Prefix update algorithms
398(5)
Performance
403(1)
References
404(5)
APPENDIX SONET AND ATM PROTOCOLS
A.1 ATM Protocol Reference Model
409(1)
A.2 Synchronous Optical Network (SONET)
410(13)
A.2.1 SONET sublayers
410(2)
A.2.2 STS-N signals
412(2)
A.2.3 SONET overhead bytes
414(3)
A.2.4 Scrambling and descrambling
417(1)
A.2.5 Frequency justification
418(1)
A.2.6 Automatic protection switching (APS)
419(2)
A.2.7 STS-3 versus STS-3c
421(1)
A.2.8 OC-N multiplexer
422(1)
A.3 Sub-Layer Functions in Reference Model
423(2)
A.4 Asynchronous Transfer Mode (ATM)
425(4)
A.4.1 Virtual path/virtual channel identifier (VPI/VCI)
426(1)
A.4.2 Payload type identifier (PTI)
427(1)
A.4.3 Cell loss priority (CLP)
428(1)
A.4.4 Pre-defined header field values
428(1)
A.5 ATM Adaptation Layer (AAL)
429(10)
A.5.1 AAL type 1 (AAL1)
431(2)
A.5.2 AAL type 2 (AAL2)
433(1)
A.5.3 AAL types 3/4 (AAL3/4)
434(2)
A.5.4 AAL type 5 (AAL5)
436(2)
References
438(1)
Index 439

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